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Your search returned 14 records. Click on the hyperlinks to view further details of Titles.. |
Magazine Name : Ieee Transactions On Circuits And Systems-Ii: Express Briefs (Formerly: Analog & Digital Signal Processing)
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Year : 2003 Volume number : 50 Issue: 11 |
Jitter Transfer Analysis Of Tracked Oversampling Techniques For Multigigabit Clock And Data Recovery
(Article)
Subject:
Clock And Data Recovery (Cdr)
,
Effective Phase Detector Gain
Author:
Youngdon
Choi
Wonchan
Kim
Deog-Kyoon
Jeong
page:
775
-
783
On The Analysis Of Fractional N Frequency Synthesizers For High Spectral Purity
(Article)
Subject:
Phase Noise
,
Monolithic
Author:
M. S. J
Steyaert
Bram De
Muer
page:
784
-
793
Techniques For In Band Phase Noise Reduction In Synthesizers
(Article)
Subject:
Bluetooth
,
Radio
,
Sigma-Delta
Author:
Thomas A D
Riley
Norman M
Filiol
Qinghong
Du
page:
794
-
803
A Behavioral Modeling Approach To The Design Of A Low Jitter Clock Source
(Article)
Subject:
Phase Noise
,
Phase Jitter
,
Phase-Locked Loop (Pll)
Author:
Sung-Ung
Kwak
Gabriele
Manganaro
Seonghwan
Cho
page:
804
-
814
Digitally Controlled Oscillator (Dco) Based Architecture For Rf Frequency Synthesis In A Deep Submicrometer Cmos Process
(Article)
Subject:
Digital Control
,
Frequency Synthesizer
,
Digital Compensation
Author:
Khurram
Muhammad
R. B.
Staszewski
Dirk
Leipold
page:
815
-
828
Phase Noise Cancellation Design Tradeoffs In Delta Sigma Fractional N Plls
(Article)
Subject:
Synthesizer
,
Phase-Locked Loop (Pll)
Author:
Sudhakar
Pamarti
I
Galton
page:
829
-
838
A Fractional N Frequency Synthesizer Architecture Utilizing A Mismatch Compensated Pfd/Dac Structure For Reduced Quantization Induced Phase Noise
(Article)
Subject:
Phase Noise
,
Frequency Synthesizers
,
Sigma-Delta Modulation
Author:
Micheal H.
Perrott
Scott E
Meninger
page:
839
-
849
Analytical Model And Behavioral Simulation Approach For A Fractional N Synthesizer Employing A Sample Hold Element
(Article)
Subject:
Linear Systems
,
Phase-Locked Loops
,
Sigma-Delta Modulation
Author:
Erik
Bruun
Marco
Cassia
Peter
Shah
page:
850
-
859
Design Of Cmos Adaptive Bandwidth Pll/Dlls A General Approach
(Article)
Subject:
Phase-Locked Loop (Pll)
,
Delay-Locked Loop (Dll)
,
Adaptive Bandwidth
Author:
Mark A
Horowitz
Gu-Yeon
Wei
Jaeha
Kim
page:
860
-
869
Methodology For On Chip Adaptive Jitter Minimization In Phase Locked Loops
(Article)
Subject:
Phase-Locked Loop (Pll)
,
Adaptive Bandwidth Pll
,
Timing Jitter Minimization
Author:
Mozhgan
Mansuri
Chih-Kong Ken
Yang
Ali
Hadiashar
page:
870
-
878
Analysis Of Pll Clock Jitter In High Speed Serial Links
(Article)
Subject:
Phase Noise
,
Jitter
,
Serial Links
Author:
Pavan Kumar
Hanumolu
Bryan
Casper
Gu-Yeon
Wei
page:
879
-
886
Just In Time Gain Estimation Of An Rf Digitally Controlled Oscillator For Digital Direct Frequency Modulation
(Article)
Subject:
Calibration
,
Frequency Synthesizer
,
Modulator
Author:
R. B.
Staszewski
Dirk
Leipold
Poras
Balsara
page:
887
-
891
A Dual Slope Phase Frequency Detector And Charge Pump Architecture To Achieve Fast Locking Of Phase Locked Loop
(Article)
Subject:
Fast Locking
,
Dual-Slope
,
Phased-Locked Loop (Pll)
Author:
Cheng-Ming
Ying
Kuo-Hsing
Cheng
Wei-Bin
Yang
page:
892
-
895
A False Lock Free Clock/Data Recovery Pll For Nrz Data Using Adaptive Phase Frequency Detector
(Article)
Subject:
Phase-Locked Loop (Pll)
,
Clock And Data Recovery (Cdr)
Author:
H
Kunieda
Gijun
Idei
page:
896
-
900
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